The goals of the faulttolerance techniques are to minimize the hardware, timing, and power overhead, and maximize the reliability of the system. Workshop on faultinjection and faulttolerance tools for. Fault tolerance techniques for sram based fpgas frontiers. The redundant circuit is too big to download onto the fpga, since methods. Pdf a framework for fault tolerant real time systems. Fault tolerance rft that enables fpgabased systems to change at runtime the amount of fault tolerance being used. An efficient berbased reliability method for srambased. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the highlevel description, without modification in the fpga architecture.
Mitigation of scu and mcu effects in srambased fpgas. General sram based fpga interconnect structure figure1 shows a detailed structure of interconnect. Sram based fpgas are sensitive to transient faults, so called soft errors, which. A generic methodology to compute design sensitivity to seu. Triple modular redundancy tmr has been successfully applied in fpgas to mitigate transient faults, which are likely to occur in space applications. This new method is capable of correcting multiple bit. Survey of soft error mitigation techniques applied to.
Faulttolerance techniques for srambased fpgas request pdf. High seu tolerance is essential for fpgas used in critical applications. However, the lack of hdl examples and the use of nearobsolete devices restrict its practical application. To further reliability assurance of the crc checker circuit, it is implemented in the auxiliary fpga using the tmr technique. Analysis of the critical bits of a riscv processor. However, selecting these techniques statically at design or compile time tends to be pessimistic and. A novel approach for providing fault tolerance to fpgabased. Designing and testing faulttolerant techniques for sram. Oct 16, 2014 different fault tolerance techniques can be applied to fpgas according to their type of configuration technology, architecture and target operating environment. However, fault tolerance techniques might introduce addi.
Abstractrecently, srambased fpgas are widely used in aeronautic and space systems. Many investigations for fault mitigation on fpgas have been conducted by researchers to enhance the reliability of srambased fpgas. Sram memory cells, srambased fpgas are also sensitive to radiation and require protection to work in harsh environments. Assessing scrubbing techniques for xilinx srambased. Our work targets scientific applications operating on spacebased fpga.
They often do not execute the scrubbing process in the right instant. However, the technique not only masks faults but also it is able to correct them. These error mitigation techniques are used to improve the reliability of fpga systems. Systemc language reference manual was published early in 2012 iee12. Srambased fpgas, the state of connections in these routing devices is controlled by sram cells, which are. Sram based fpgas are susceptible to atmospheric radiation. Columnbased precompiled configuration techniques for fpga. Several faulttolerant methods to tolerate seu effects have been proposed previously.
Some example of these techniques, are triple modular redundancy tmr 7 and duplication with comparison with concurrent error detection dwcced 8. An seu occurring in one of the configuration bits of the fpga may cause a permanent error. An efficient berbased reliability method for srambased fpga. Criticalityaware scrubbing mechanism for srambased fpgas. Fault tolerant circuits on sram based fpga can be imple mented by two.
An adaptive faulttolerant memory system for fpgabased. This paper discusses high level techniques for designing fault tolerant systems in srambased fpgas, without modification in the fpga architecture. The xilinx virtex5qv is the rst commercially available radiation hardened by design rhbd srambased fpga. The effects of the space environment on fpga include total dose effect and single event effect see.
Srambased fpgas can be considered a twolayer device. Seus in srambased fpgas have made reliability a major concern for fgpa users. Faulttolerance techniques for srambased fpgas fernanda. Fault tolerant techniques can detect the faults and correct them, or mask the faults. Faulttolerance in integrated circuits is not an exclusive concern regarding space designers or highlyreliable application engineers. In this work, we try to mitigate the effects of seus in sram based fpgas. Fpgabased reliable fault secure design for protection.
Seu fault evaluation and characteristics for srambased. Dynamic heavy ions see testing of nanoxplore radiation. Soft error rate estimation and mitigation for srambased. Characterization of designs and fault tolerance veri. Comparision of ft techniques used for fpgas the design exploration process of an application must be able to weigh the pros and cons of different ft methodologies on factors such as system performance, cost. On the design of tunable fault tolerant circuits on sram. Srambased fpgas are sensitive to transient faults, so called soft errors, which. We present a fault tolerance technique for transient and permanent faults in sram based fpgas. The presented method in 2 is an approach based on the tmr technique. This paper discusses faulttolerant techniques for srambased fpgas.
This section motivates the need for protection with a discussion on fault modes in srambased fpgas. Fpga is a highdensity srambased that is not susceptible to seu. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. Need for ft for fpgas fault tolerance is defined as the ability of a system to operate normally given the presence of malfunctioning resources, or faults 2. This book discusses faulttolerance techniques for srambased field programmable gate arrays fpgas. They can be handled through fault tolerance techniques like scrubbing and modular redundancy. Faulttolerance techniques for srambased fpgas, the computer. Framelevel redundancy scrubbing technique for sram. Hardware and software faulttolerance of softcore processors. Fault tolerance designing faulttolerant techniques for sram.
The aim of this work is to investigate the feasibility of using xilinxs srambased fpgas with triple modular redundancy tmr and scrubbing techniques for space applications. The technique is based on the classical tmr solution that is used to mask functional errors in a design. An adaptive method to tolerate soft errors in srambased fpgas. Faulttolerance techniques for srambased fpgas, the. Reassuring fault tolerance in computing systems is an important problem in highreliability applications. We present a fault tolerance technique for transient and permanent faults in srambased fpgas. Read download fault tolerance techniques for sram based. Designing faulttolerant techniques for srambased fpgas ieee. Fault injection by hardware techniques in fpgas though the principles remain the same, the setups and algorithms might differ as the technology provides better solutions. Mbu can be up to 10% of the total bitflips observed in the configuration memory bits of an fpga fabricated in 28nm technology 2. This paper discusses fault tolerant techniques for sram based fpgas. Fpga, reconfigurable fault tolerance, single event upsets. Faulttolerant circuits on srambased fpga can be imple mented by two.
Mccluskey center for reliable computing department of electrical engineering stanford university, stanford, ca 94305. Faulttolerant techniques, such as triplemodular redundancy tmr and memory scrubbing, can protect the system from most seus and signi. Pdf fault tolerant reconfigurable hardware design using bist on. The software faulttolerance techniques used to protect the logic and routing of the leon3 softcore processor include a modi. Some of these are based on new faulttolerant architecture, and others on protecting the highlevel. Chapters 8 and 9 present some techniques that can be used to reduce the area overhead of a mitigated design, exchanging hardware redundancy for time redundancy, where applicable. Section iii explains types of faults and fault models.
Section iv gives the fault detection technique and simulation results and concludes with section v. Sram based fpgas such as actel antifuse fpgas since they provide much lower susceptibility to soft errors compared to srambased fpgas. Read download fault tolerance techniques for sram based fpgas. Section 2 describes how softerrors corrupt the operation of srambased fpgas. This thesis is about managing srambased fpga faults at system level, in the context of. Online testing and recovery of systems on srambased fpga. Fault tolerance techniques for sram based fpgas frontiers in. As the adverse effects of radiations in space are much higher than in the earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. Jan 27, 2017 this chapter focuses on problems face by fpga space applications and fault. Sram based fpgas allow engineers to perform product improvements by rewriting the configuration data. It begins by discussing the effects of radiation on electronics in general and then identi. These techniques come at the cost of time instead of area. This thesis is about managing sram based fpga faults at system level, in the context of. Soft error rate and fault tolerance techniques for fpgas.
Fault tolerance in integrated circuits is not an exclusive concern regarding space designers or highlyreliable application engineers. Assessing scrubbing techniques for xilinx srambased fpgas in. Fault tolerant techniques are often used to mitigate these problems. This chapter will present a set of fault mitigation techniques for sram, flash and antifusebased fpgas and a test methodology to characterize those fpga under radiation. Columnbased precompiled configuration techniques for fpga fault tolerance weije huang and edward j. A clb also contains flipflops, multiplexers, and dedicated circuitry to optimize the performance of user applications. A new reconfigurable clockgating technique for low power. Tmr triple modular redundancy is a classic technique using redundancy to reduce the faultinduced failures, but is known to have high overhead in area, power and performance. Sep 01, 2019 therefore, in order to employ srambased fpgas in harsh environments, such as space, radhard by design rhbd techniques are frequently adopted to increase the robustness level of those fpgas. Several fault tolerant methods to tolerate seu effects have been proposed previously. Framelevel redundancy scrubbing technique for srambased fpgas. With the interest in commercial srambased fpgas in radiation environments, it is beneficial to provide runtime reconfigurable recovery from a failure. There have been extensive studies to mitigate the impact of seu on cram bits.
As a result, mbu events in srambased fpgas are increasing in newer devices. Some of these are based on new faulttolerant architecture, and others on protecting the highlevel hardware description before synthesis in the fpga. Request pdf faulttolerance techniques for srambased fpgas faulttolerance in integrated circuits is no longer the exclusive concern of space designers or highlyreliable applications engineers. Fault tolerant design implementation on radiation hardened. Worldknown fpgabased companies, such as atmel 2 and xilinx 3 are traditional suppliers of radhard srambased fpgas to space missions. This technique reduces the number of io pads, and therefore power dissipation, in the interface. Aug 08, 2016 fault tolerance within sram based fpgas for aerospace applications abstract. Faulttolerance techniques for srambased fpgas ebook, pdf. Seu fault evaluation and characteristics for srambased fpga. Faultmitigation strategies for reliable fpga architecture halinria. A generic methodology to compute design sensitivity to seu in.
Overview of fault tolerance techniques and the proposed tmr. Fault tolerant design implementation on radiation hardened by. Columnbased precompiled configuration techniques for. This chapter focuses on problems face by fpga space applications and fault. Clbs are connected through horizontal and vertical wiring channels between two neighboring rows or. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. Comprehensive coverage of all aspects of space application oriented fault tolerance techniques experienced expert author working on fault tolerance for chinese space program for almost three decades initiatively provides a systematic texts for the cuttingedge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge presents. Fault tolerance within sram based fpgas for aerospace.
In short, faulttolerance techniques for srambased fpgas may be a good starting point for a reader seeking to familiarize with the subject of faulttolerance. Designing and testing faulttolerant techniques for srambased. However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the fpga. Software fault tolerance methodology and testing for the. Fault tolerance techniques are categorised into three main classes. Soft error rate estimation and mitigation for srambased fpgas.
Designing fault tolerant systems into srambased fpgas. Pdf a framework for fault tolerant real time systems based. Traditional fpga fault tolerance techniques, such as scrubbing and tmr, cannot be applied to the embedded powerpc. Luca sterpone workshop on faultinjection and faulttolerance tools for reprogrammable fpgas, 2009, esaestec, noordwijk, the netherlands goal to provide solutions for increasing the faulttolerance capabilities with algorithms able to reduce sensitive configuration memory bits of srambased fpgas. Abstractin this paper we describe our softwarebased fault tolerance strategies for powerpc devices embedded within xilinx virtex 4 fx60 fpgas. A new fault injection approach to study the impact of. Fpga, reconfigurable fault tolerance, singleevent upsets. Faultinjection and fault tolerance tools for reprogrammable fpgas 12 v3. In srambased fpgas, a clb contains several sram lookup tables luts to store userdefined logic functions. A novel approach for providing fault tolerance to fpga.
Several techniques have been developed in order to reduce the power consumption of reconfigurable fpgas. This technique reduces the number of io pads, and therefore power dissipation, in the interface compared to. Detection and diagnosis of faults in the routing resources of. Triple modular redundancy tmr has been successfully applied in fpgas to mitigate transient faults, which are likely to. These techniques can be based on circuit level modifications, with obvious. Due to their inherent configurability, fpgas srambased field programmable gate arrays are especially suitable for the implementation of modular fpgas.
The configuration memory cells are however susceptible to ionised particles which upon impact can cause the memory cell to change state. Srambased fpgas are highly attractive for space applications due to their inight recon gurability, decreased development time and cost, and increased design and testing exibility. Pdf towards supporting faulttolerance in fpgas dionisios. Our highlevel fault tolerance tech nique combines time and hardware redundancy to cope with upsets in sram based fpgas. Designing faulttolerant techniques for srambased fpgas. Fault tolerance designing faulttolerant techniques for. The top layer is composed of the logic and memory resources. Overview of fault tolerance techniques and the proposed. In this paper a virtual coarsegrained reconfigurable architecture is proposed, with an embedded ondemand faultmitigation technique. Detection and diagnosis of faults in the routing resources. Towards supporting faulttolerance in fpgas kostas siozios and dimitrios soudris dionisios pnevmatikatos school of electrical and computer engineering electronic and computer engineering department national technical university of athens, greece technical university of crete, greece email. The redundant circuit is too big to download onto the fpga, sin.
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